Intel boosts Penryn and Nehalem performance

Intel is promising a 20 to 45 per cent performance improvement for its upcoming 45nm Penryn processors due out later this year.  

An additional performance boost will follow in 2008 when the chipmaker starts shipping its Nehalem micro-architecture.

"We view Nehalem as the first truly dynamically scalable micro-architecture, " Pat Gelsinger, general manager of Intel's Digital Enterprise Group, said at a meeting with reporters in San Francisco.

Intel develops new core architectures on a two-year schedule. The current Core architecture was released in March 2006.  

"The Core micro architecture is built for 45nm and 65nm. In the case of Nehelam, it is natively architected to take full advantage of 45nm," said Gelsinger.

"In that sense it is really going unlock the full potential of that process technology's capabilities beyond what the Penryn was capable of doing."

Nehalem will introduce two processing threads for each core, up from the current single threaded cores. Intel is currently working on eight-core processors, but might introduce larger chips in the future.

Mimicking the design of AMD processors, Nehalem will embed the memory controller onto the chip. It is currently part of the front side bus. In another move that follows AMD's lead, Nehalem will deliver an integrated graphics processor. 

Intel declined to say whether the GPU is integrated in the chip package or part of the die.

The last option offers better performance and energy consumption, but could result in lower yields during chip manufacturing because it increases the die size.

Nehalem chips will not offer all of the available features, warned Gelsinger. It is therefore unlikely that an eight-core processor will come with the integrated graphics processor.

The Nehalem micro-architecture is scheduled to start shipping in 2008. Intel plans to release its first 45nm Penryn chips later this year.

The chipmaker has said that Penryn will come in two-core and four-core versions, and will be the first chip to feature the new SSE4 instruction set.  

Penryn will also use a new transistor design that dramatically cuts power leakage.

Gelsinger unveiled additional improvements to the Core micro architecture at the media briefing that will boost performance while cutting power consumption.

The new chip will offer on-chip caches of 12MB for a quad-core chip, for instance, and 6MB for a dual-core model. Current dual-core chips feature a 4MB cache.

The larger memory size will boost performance for certain applications and enable a new power saving feature dubbed 'Deep Power Down', in which all clocks and caches are powered down completely and the data the they contain is temporarily stored to a special location on the chip's die.

Intel will also introduce enhancements to the on-chip virtualisation technology which cuts the time it takes to get into and out of a virtual machine by 25 to 75 per cent, Gelsinger said.

An updated Dynamic Acceleration Technology promises to advance non-threaded applications into the multi-threaded age.

Software developers have to specially design their software to run on multi-core and multi-threaded processors by allowing calculations to be divided between multiple threads or cores.

Most of today's consumer desktop applications lack such features. The Penryn processor, however, will notice when one core is fully used while another is sitting idle, and will move part of the workload to the unused core.

The performance gains between upcoming Penryn systems and current generation 65nm chips depend on the application. Early tests demonstrated at least a 20 per cent improvement, according to Gelsinger.

The new SSE4 instruction set allows multimedia applications to perform more than 40 per cent better.

Increases in the cache sizes and a faster front side bus, meanwhile, will primarily benefit high performance computing and floating point applications, leading to 45 per cent performance boosts.

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